Due to the constant shrinking of the critical dimensions in ULSI (ultra large scale integrated) circuits in order to improve speed, functionality and cost, delay and crosstalk related to the interconnection part of the circuit become limiting factors for speed and logical performance. The relatively recent move from Aluminium to Copper interconnects has yielded a 30% reduction in the resistance of wired connections on a chip.
Referring to FIG. 1 of the drawings, after a first copper metallization 23 has been formed in a dielectric layer 18, an inter-metal dielectric layer 25 is formed over the first copper metallization. When a via 27 or dual damascene opening is made through the inter-metal dielectric layer 25 to the underlying first copper metallization 23, some of the underlying copper is sputtered away and re-deposited (at 29) onto the sidewall of the via 27 or dual damascene opening. This causes contamination of the inter-metal dielectric layer 25. This problem arises when the copper lines are opened during and after the via etch. The SiC or SiCN barrier (not shown), which is usually used as a cap layer on top of the copper lines, has to be opened very carefully to avoid re-sputtering of the Cu on the sidewalls of the via.
In addition, during ash and cleaning of the opened vias, Cu contamination can easily occur, especially when an Argon RF-based pre-clean is employed, a significant amount of Cu re-sputtering on the via sidewall occurs. A reactive pre-clean (RPC) based on He/H2 DC plasma is able to reduce CuO on the bottom of the vias with a minimum amount of re-sputtering. However, the removal of polymer residues is more of a problem with RPC, and potentially results in a loss of yield.
Therefore, a so-called “barrier fit” integration process has been proposed, in which the above-mentioned pre-clean step can be omitted. After via opening, a metallic barrier is deposited, followed by a re-sputter step to remove all barrier residues, where present, and any copper oxide at the bottom of the via. An additional thin barrier is then deposited to cover the unlanded or misaligned vias. However, the Cu contamination problem still remains during the via etching step.
European Patent Application No. EP-A-1102315 describes a method of preventing copper contamination of the inter-metal dielectric layer during via or dual damascene etching, in which a conductive capping layer is deposited overlying a copper metallization formed in a first inter-metal dielectric layer and overlying the surrounding first inter-metal dielectric layer. The capping layer is then removed except from the copper metallization and a second inter-metal dielectric layer is deposited over the capping layer, and a via is etched through the second inter-metal dielectric layer to the capping layer, such that the capping layer prevents contamination of the second inter-metal dielectric layer during etching. However, this type of barrier faces selectivity issues, since any metallic deposition in-between metal lines may increase capacitive coupling in-between metal lines, and additional integration development is required.
It is known in the art, if a barrier is selectively deposited on top of the metal lines as in the method described in EP-A-1102315, instead of the conventional full sheet SiC or SiCN films, the potential Cu contamination during via etching can be avoided. In addition, a significant improvement in the capacitive coupling can be achieved because the SiC or SiCN capping and etch stop layer is omitted.
Current integration schemes of self-aligned metallic barriers are mostly based on selective processes such as metallic Tungsten CVD or electrolessly deposited alloys (CoWP, etc). These barriers should have a barrier performance as good as the conventional dielectric capping in terms of adhesion and mechanical strength, resistance to stress-induced voiding and electromigration, with an effective efficiency against copper diffusion and corrosion. Although the electroless deposited films show improved reliability performance compared to a SiC capping and the like, a fairly thick film needs to be deposited to obtain the desired Cu diffusion barrier properties. Moreover, these barriers also face selectivity issues, since (as explained above) any metallic deposition in-between metal-lines may further degrade leakage current properties and additional integration development is required. In addition, the electroless grown films generally tend to grow in a lateral direction thereby reducing the dielectric spacing and increasing the capacitive coupling between the lines. As an alternative, a novel barrier (CuSiN) has recently been proposed that is based on copper surface modification, which alleviates the selectivity concern, while being equivalent in terms of propagation performances to other selectively deposited barrier techniques. The main concern with this approach remains the potential Cu re-sputtering on the via sidewalls prior to barrier deposition and the potential increase of line resistance.